Various approaches exist for receiving and converting an input radio frequency (RF) signal to a desired frequency. Of particular interest are direct conversion receivers. A direct conversion receiver mixes directly to a baseband signal without converting the input RF signal to an intermediate frequency, as is the case in a superheterodyne receiver. That is, a direct conversion receiver converts the incoming radio signal to baseband in a down-conversion step, wherein an associated local oscillator operates at a frequency that coincides with the center of the input RF signal. Direct conversion receivers can be implemented in connection with various communications protocols, such as, for example, the Universal Mobile Telecommunications System (UMTS), General Packet Radio System (GPRS) and Global System for Mobile (GSM)-based wireless communications devices and the like.
For reasons of lowered cost, improved yield and lower power dissipation, most of the receiver gain usually is implemented in a baseband section of the receiver by the use of amplifiers. In order to compensate for large variation in received signal amplitude in wireless environments, the receiver gain usually is variable.
DC offsets are inherent in any amplifier and can arise from sources such as device mismatches. If amplifier stages in a receiver are DC coupled, the receiver can saturate due to the DC offset of the amplifiers. In order to implement a high gain in baseband, it thus becomes important to AC couple the amplifier stages. For example, if the baseband gain is 60 dB, and the input offset on the first amplifier in the baseband is 10 mV, and the supply voltage is 3 V, the output will be limited to the supply, and, if the amplifiers are DC coupled, the receiver would not be able to provide desired linear amplification of the input signal. This would be unsatisfactory in a receiver.
AC coupling can be accomplished either by placing explicit active high-pass filers in between the amplifiers, or otherwise by simply using coupling capacitors in between gain stages. In either case, the filter is characterized by a zero at DC and a pole at the high-pass transition corner of the filter. This corner generally cannot be made too large, as the down-converted signal itself is at DC. Hence, as the corner frequency is increased, there is a corresponding loss in signal power. The corner frequency thus can be set by determining an acceptable signal loss at low frequencies. For example, in WCDMA (Wideband Code Division Multiplexing) systems, the signal bandwidth is approximately 2 MHz. Accordingly, a high-pass corner frequency of about 10 kHz would be acceptable.
A problem with such a low high-pass corner frequency is that the settling response time of the filter may not be acceptable. By way of illustration, continuing with the above example having a baseband gain of 60 dB, assume that the amplifier is implemented as a cascade of three capacitively coupled variable gain amplifiers, each providing a maximum gain of 20 dB, where each capacitor has an associated high-pass corner of 10 kHz. If the input offset in such a case is 10 mV, and the gain of the input amplifier is switched from 0 to 20 dB, this would cause an instantaneous glitch of about 100 mV at the output of the first amplifier, a 1 V glitch at the output of the second amplifier, and drive the third amplifier into saturation (e.g., a clipped state). For purposes of this example, assume linear settling, which provides a settling time for the amplifiers of about 300 μS (assuming an acceptable settling performance of 3t, where t is the time constant of the filter). The implication of the above is that for a period of several ten or hundreds of microseconds, after application of a gain control command, the output is unusable. By most conventional communication standards, this would be unacceptable.
A known technique around this problem is to anticipate the application of the gain control step and to temporarily increase the high-pass corner frequency of the filter, known as a speed-up mode. The temporary increase in the corner frequency enables glitches generated by the gain step to settle more quickly. After the glitch settles, the filter is returned to its original state that has a low-corner frequency.
FIG. 1 illustrates a conventional implementation of a direct conversion receiver 10 implementing a speed-up mode. The receiver 10 includes a DSP 12 that provides a speed up control signal 14 to the analog section 16 via a control line to implement desired speed-up mode control. The speed-up control signal 14 is provided to high-pass filters 18 of the analog section 10. The DSP 12 also provides a gain control signal 20 to amplifiers 22 of the analog section 12 via a separate control line to implement variable gain control. Each control line usually requires a separate pin on the integrated circuitry. The analog section 16 provides output signal to the DSP 12 through associated A/D converters 24. The receiver also includes a receiver front end 26 that receives an input RF signal from an antenna 28. Because the gain control is determined in the DSP 12, the DSP can anticipate its application and provide suitable control information to the analog filters to implement desired speed-mode.
An example of a timing diagram for signals provide on control lines from the digital section is shown in FIG. 2. The gain control signal Vgc is illustrated as three levels. The speed-up control signal is illustrated as including a pulse with a high level for each change in gain control signal Vgc.